Accelerating Matrix Processing for MIMO Systems

Massive Multiple In and Multiple Out (MIMO) is being used in the fifth generation of wireless communication systems. As the number of antennas increases, the computational complexity grows dramatically, and this involves matrix calculations with complex numbers. We have designed and implemented a general matrix arithmetic processor to accelerate these calculations, including matrix multiplication, Singular Value Decomposition (SVD), and QR decomposition, on an FPGA. The design can be implemented in fixed-point or single-precision floating-point depending on the requirements of the application. The system behavior can be controlled by instructions such as elementary multiplication, rotation and vector projection, which allows the system to work as a coprocessor in a baseband System on a Chip (SoC). Latency for changing from one matrix computation to another is just a few clock cycles, providing the low latency required for edge processing. The design is implemented and verified on the Xilinx RFSoC development board using fixed point and single precision floating point numbers and matrix sizes of 8 X 8 and 16 X 16.