A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool

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Although a multi-FPGA system receives attention as a server for MEC (Multi-edge access Computing), traditional design tools only focuses on a single FPGA. Here, a multi-FPGA programming environment based on NEC's integrated design tool CyberWorkBench (CWB) is introduced for a multi-FPGA system FiC (Flow-in-Cloud). Programmers describe their program in SystemC as small modules connected with FIFO channels, then verify the operation with the behavioral simulation considering parallel execution. After the high level synthesis (HLS) is done with CWB, modules distributed to each board is decided, and interface module is inserted. The cycle accurate simulation is applied to ensure the operation and estimate the performance. Finally, generated Verilog HDL code for each board is implemented with Xilinx's Vivado just like the traditional design and configuration is obtained. As an example, a simple convolutional neural network LeNet is described, and implemented on a real system using the tool. Although the cycle accurate simulation takes 105.34sec, the estimated cycles is only 2.2% difference of the real boards execution result. Since the example CNN LeNet is too small, it can be implemented into a single board with traditional design tool.
However, considering the pipeline execution, parallel execution with two boards can distribute the input and output into different FPGAs, and relax the bottleneck.

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