Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks

OpenCL-based HLS frameworks are known to reduce the development effort for FPGAs while offering good quality results. The upcoming trend to equip heterogeneous compute clusters with hy- brid networks for inter-CPU and inter-FPGA communication allows scaling FPGA workloads beyond a single FPGA. However, there is no tool for performance characterization of those FPGA-accelerated systems and their communication networks yet.
To fill this gap, we implemented a parametrizable OpenCL bench- mark suite for FPGA based on the HPC Challenge for CPU. In the first step, we showed that the parametrization of the benchmarks al- lows high quality of results on Intel and Xilinx FPGAs. In the future, we plan to extend the benchmarks to scale over multiple FPGAs to create a performance characterization tool for HPC multi-FPGA systems and further investigate the opportunities and limitations of different inter-FPGA communication approaches.

Speaker: Marius Meyer